This invention relates to semiconductor fabrication, and more specifically to power MOSFET contact fabrication.
UBM: under-bump metal, the conductive metal used to connect a source or gate contact to an external circuit via a surface solder bump.
Conductive bumps provide an interconnect between an active semiconductor device and a package which then is placed into an application. Discrete Field Effect Transistors (FETs) usually have at least 3 connections: (1) a control gate; (2) a drain; and (3) a source. The drain is usually the back side of a die and the entire back side of the die is mechanically and electrically connected to the package. The source is usually on the front side of the die and has several bumps, which provide mechanical and electrical contact to the package. The control gate traditionally has only a single bump connected to the contact of the package on the front side of the die. The use of a single bump for the gate connection creates a significant probability of gate connection failure due to mechanical stress. This contrasts with a lower probability of such failure for a source connection, which has multiple bumps that continue to operate if any one of them fails. To put more bumps on a gate pad would reduce the likelihood of gate connection failure, but it would require a larger gate pad and therefore more area for the total die, increasing the cost of manufacturing the device.
See FIG. 1, showing a cross section of the gate area of a prior art device. Gate bump 10 is fabricated directly above gate metallization 50, gate contact 51, and under bump metal 52 and 53, to make an external contact between gate metallization 50 of wafer 7 and package control gate connection 5, via connection point 54. Source bumps 11, 12 are fabricated directly above source metallization 60, source contact 61, and under bump metal 62 and 63, to make an external contact between source metallization 60 of wafer 7 and package source connection 6, via connection points 64. An insulating layer 40 provides electrical isolation between gate and source circuitry. A second insulating layer 90 provides added isolation and external protection.
FIG. 2 shows the prior art approach in plan view. To simplify FIG. 2 without omitting essentials of the invention, the SiO or SiN passivating layers over gate and source metallizations are not shown in the figure. The single package control gate connection 5 connects at contact point 54 over bump 10, with no additional mechanical support for the gate connection.
The single gate bump 10 represents a single point of failure for the entire device. Gate bump 10 is the sole point of contact for package control gate connection 5, at connection point 54. If mechanical stress causes delamination of under bump metal 52 or 53, the gate connection will fail. Some means of reducing the mechanical stresses on the gate bump connection is needed.
The invention provides a more robust mechanical connection between a semiconductor device and the device package by adding one or more bumps to the gate connection without adding more gate pad area. The invention first provides a nonconductive layer covering the area around the gate pad and extending over the source area. The invention adds one or more bumps on the nonconductive layer to provide mechanical strength and support to the gate pad connection. The added bumps are not electrically connected to either the gate or the source. The package connections must be altered, both to fit the added bumps on the control gate, and to connect with fewer bumps on the source.